In testing a semiconductor integrated circuit device by a semiconductor test system, the semiconductor IC device to be tested (device under test or DUT) is provided with test signals and the resultant output signals of the device under test are compared with expected value signals prepared in advance to determine whether the intended functions of the device under test is performed correctly.
Such a test signal is supplied to each pin of the device under test from a driver circuit via a transmission cable. The driver circuit functions as a buffer amplifier whereby providing a predetermined amplitude to the test signal. The resultant output signal of the device under test is compared with the expected value by a comparator. A large number of sets of driver circuits and comparators are assembled in a pin electronics unit in the semiconductor test system. To protect both the driver circuit and comparator as well as the device under test from excessive voltages caused by various factors, a voltage protection circuit is usually provided in connection with the driver circuit and comparator.
An example of conventional circuit diagram of a voltage protection circuit in a semiconductor test system is shown in FIG. 2. This example shows that the protection circuit is employed at the connection point between the comparator and the transmission cable (output of DUT). In this example, the protection circuit functions as both an excessive voltage clamp circuit and an abnormal voltage detection circuit. The operation of the circuit arrangement of FIG. 2 is explained with reference to FIGS. 2-5.
In the conventional example of FIG. 2, the main portion of the excessive voltage clamp circuit and the abnormal voltage detection circuit includes diodes D1-D8, buffer amplifiers OP1-OP4, comparators CP1 and CP2, and switches SW1, SW4 and SW5. A comparator 90 is provided to compare the output signal of the DUT which is resulted from a test signal provided to the DUT through a driver (not shown). Similar protection circuit can be arranged at the output of the driver circuit.
The excessive voltage clamp circuit clamps an excessive voltage in the output voltage of the DUT. The abnormal voltage detection circuit detects an abnormal voltage which is larger than the excessive voltage and opens the switch SW1 to disconnect the comparator 90 from the DUT.
First, the operation of the excessive voltage clamp circuit is explained. The excessive voltage clamp circuit comprises the diodes D3, D4, D7 and D8, the buffer amplifiers OP1 and OP2, and switches SW1, SW4 and SW5.
The switch SW1 remains closed (ON) when the clamping operation is performed. Also, the switches SW4 and SWS remain closed (ON) when clamping operation on the output voltage from the DUT is performed.
The operation of the clamp circuit is explained with reference to a simplified circuit diagram of FIG. 3. In FIG. 3, only fundamental components are shown while omitting the buffer amplifiers OP1 and OP2 and diodes D3 and D4 therefrom for simplicity of explanation. The switches SW4, SW5 are turned on when the clamping operation is carried out and are turned off when the clamping operation for the output voltage of the DUT is not performed.
Thus, in FIG. 3, the excess voltage clamp circuit is basically configured by the switches SW4 and SW5 and the diodes D7 and D8. The connection point of the diodes D7 and D8 is commonly connected to the input of the comparator 90 which receives the output signal of the DUT through the transmission cable 200. Clamp voltages VH and VL in FIG. 2 are set to define the high level clamp voltage and the low level clamp voltage, respectively.
FIG. 4(a) shows an example of a voltage waveform when the output of the DUT through the transmission cable 200 is not clamped. As noted above, generally, a device under test (DUT) has a plurality of terminal pins, and each terminal pin is connected to the pin electronics unit having a comparator and a driver circuit, etc., through a corresponding transmission cable 200.
The transmission line 200 is so structured to have a characteristic (transmission) impedance, which is for example, 50 ohms. The impedance of the transmission cable is designed to match with the impedance of the terminal pin of the DUT to achieve an accurate test result in a high frequency range. However, a semiconductor test system needs to test various types of DUTs, and thus, the output impedance at a terminal pin of a DUT does not necessarily match with the impedance of the transmission cable.
For example, when the output impedance of the DUT is smaller than the impedance of the load (input of the comparator 90), a reflection waveform is superimposed on the transmission signal as shown in FIG. 4(a). In such a case, the testing on the DUT cannot be properly performed because the output voltage of the DUT received by the comparator 90 may exceed the voltage limit of the comparator 90 or include incorrect representation of the actual DUT output signal, thereby causing a breakdown or resulting in a measurement error in the test result.
Therefore, a semiconductor test system includes a voltage protection circuit such as shown in FIG. 2 to limit the output voltage of the DUT by establishing an upper clamp voltage and a lower clamp voltage. For example, when a DUT is a TTL IC, an upper clamp voltage VH of 5V and a lower clamp voltage VL of 0V for low voltage VL will be established in the excess voltage clamp circuit.
In FIG. 3, assuming a forward bias voltage of each of the diodes D7 and D8 is Vf. As is well known in the art, such a forward bias voltage of a silicon diode is 0.7V. Thus, in the case where the clamp voltages VH and VL are 5V and 0V, for example, the diode D8 turns on when the output of the DUT becomes higher than 5V+Vf. Consequently, the voltage at the input of the comparator 90 is limited to the voltage level of 5V+Vf by flowing a current from the DUT to the clamp voltage VH through the diode D8. Conversely, the diode D7 turns on when the output of the DUT becomes lower than 0V-Vf, thereby limiting the input voltage of the comparator 90 to the voltage level of 0V-Vf while allowing the current flow from the clamp voltage VL to the DUT. As a result, the output voltage of the DUT is clamped to limit the excessive voltage as shown by the voltage waveform of FIG. 4(b).
In the basic operation involved in the configuration of FIG. 3, there arises a potential difference of Vf in the actually clamped voltage from the intended clamp voltage VH or VL because of the forward bias voltage of the diodes D7 and D8. In order to avoid the effect of the forward bias voltage Vf in the foregoing, the protection circuit of FIG. 2 is designed to compensate the voltage difference by canceling the bias voltage Vf of each of the diodes D7 and D8. Such a function is performed by using a set of a buffer amplifier OP1 and a diode D3 and a set of a buffer amplifier OP2 and a diode D4. Each of the buffer amplifiers OP1 and OP2 functions as a voltage follower.
A constant current source A3 provides a bias current to the diode D3 to produce a forward bias voltage Vf in the diode D3. Similarly, a constant current source A4 provides a bias current to the diode D4 to produce a forward bias voltage Vf in the diode D4. Under this arrangement, the voltage at the anode of the diode D7 becomes VL+Vf and the cathode of the diode D8 becomes VH-Vf. Hence, the actually clamped voltage in the output of the DUT is equal to the upper clamp voltage VH or the lower clamp voltage VL.
Although not shown in FIG. 2, the buffer amplifiers OP1 and OP2 are provided with current limit circuits to protect themselves. The clamp circuit will not perform the clamping operation if the current through the diode and the buffer amplifier exceeds the range specified by the current limit circuit. In a case where an actual output waveform of the DUT is desired to be observed, the switches SW4 and SW5 are turned off to remove the clamping operation from the output voltage of the DUT.
The operation of the abnormal voltage detection circuit is explained in the following. In the example of FIG. 2, the abnormal voltage detection circuit comprises diodes D1, D2, D5 and D6 and buffer amplifiers OP3 and OP4, switch SW1, resistors R1 and R2, and comparators CP1 and CP2.
When the output voltage of the DUT becomes an abnormal voltage, an abnormal detection signal Vs is output, which turns off the switch SW1. The operation of the abnormal voltage detection circuit is explained with reference to a simplified structure of FIG. 5. The circuit diagram of FIG. 5 shows only the main components of the detection circuit by omitting the buffers amplifiers OP3 and OP4, the diodes D5 and D6 from the abnormal voltage detection circuit in FIG. 2. Thus, the basic circuit diagram of FIG. 5 shows the comparators CP1 and CP2, the resistors R1 and R2, the current sources A1 and A2, the diodes D1 and D2, and the switch SW1.
In FIG. 5, the output voltage of the DUT is represented by Vo, and the voltage values are set for a higher abnormal threshold voltage VHH and for a lower abnormal threshold voltage VLL, respectively. For example, in order to protect the components in the semiconductor test system such as comparators and driver circuits, the higher abnormal threshold voltage VHH is set to 8V and the lower abnormal threshold voltage VLL is set to -3V.
As to the comparators CP1 and CP2, to establish a voltage difference between two inputs of each comparator, the resisters R1 and R2 are provided between the corresponding two input terminals. By supplying the constant current from the constant current sources A1 or A2 to the resisters R1 or R2, the voltage difference (reverse bias) is created between the two input terminals of each comparator. Such an intentional voltage difference (reverse bias) promotes stability of operation in the comparator. This is because if a voltage difference between the two input terminals is very small, such as zero volt, the comparator may respond to small noise, resulting in the instability of operation.
As noted above, the forward bias voltage of each of the diodes D1 and D2 is Vf. If the output voltage Vo of the DUT exceeds 8V+Vf, the diode D2 turns on and a current flows from the DUT to the threshold voltage VHH through the diode D2 and the resister R2. When the current flowing through the resister R2 and the resultant voltage drop across the resister R2 exceeds the reverse bias, the comparator CP2 is activated to produce an abnormal detection signal Vs. The switch SW1 is then turned off in response to the abnormal detection signal Vs.
Similarly, if the output voltage Vo of the DUT is lower than -3V-Vf, the diode D1 turns on and current flows from the threshold voltage VLL to the DUT through the resistor R1 and the diode D1. Thus, when the current flowing to the resister R1 exceeds the constant current, the polarity of the voltage across resister R1 is reversed, and the comparator CP1 is activated to produce an abnormal detection signal Vs. The switch SW1 is then turned off in response to the abnormal detection signal Vs to separate the DUT from the semiconductor test system.
As described in the foregoing, even when an abnormal voltage is generated in either the high voltage side or the low voltage side due to the abnormality of the DUT, for example, the semiconductor test system is protected by isolating the output of DUT from the semiconductor test system by means of the switch SW1 using the abnormal voltage detection circuit.
In the more detailed circuit diagram of FIG. 2, the abnormal voltage detection circuit further includes the buffer amplifiers OP3 and OP4, and the diodes D5 and D6. Each of the buffer amplifiers OP3 and OP4 function as a voltage follower.
A constant current source A5 provides a bias current to the diode D5 to produce a forward bias voltage Vf across the diode D5. Similarly, a constant current source A6 provides a bias current to the diode D6 to produce a forward bias voltage Vf in the diode D6. Under this arrangement, the voltage at the anode of the diode D1 becomes VLL+Vf and the cathode of the diode D2 becomes VHH-Vf. Under this arrangement, the diode forward bias voltage Vf is canceled so that the actually detected output voltage of the DUT becomes equal to the upper threshold voltage VHH or the lower threshold voltage VLL.
In the arrangement of FIG. 2, when the switches SW4 and SW5 are turned on, both the abnormal voltage detection circuit and the clamp circuit are in simultaneously operation. However, as explained in the foregoing, the current limiting circuits (not shown) are provided to the buffer amplifiers OP1 and OP2 in the excess voltage clamp circuit, and the clamp circuit will not operate when the voltage exceeds the limiting range. Thus, in such a situation, only the abnormal voltage detection circuit operates.
As explained in the foregoing, in the conventional voltage protection circuit, although the circuitry and operation are similar between the excessive voltage clamp circuit and abnormal voltage detection circuit, they are constructed independently. Thus, the number of circuit components is relatively large, resulting in high cost and a large circuit size. Therefore, there is a need to realize a more cost effective protection circuit with less cost and circuit size.